Commutation cells are commonly used in electronic systems that require conversion of a voltage source, including both DC-DC converters and DC-AC converters, which are often called inverters. With the limited space allowed for power converter circuits, such as those used for example in electric and/or electric hybrid automotive applications, and given the high cost of the semiconductors, the demand for integration of these commutation cells increases.
A known way of reducing the space occupied by semiconductors in power converter circuits is to increase their efficiency to allow the size of the cooling surface to be reduced.
Losses in power electronic switches present in conventional power converter circuits are mainly caused by two sources: conduction losses and switching losses. One way to reduce switching losses is generally by accelerating turn-on and turn-off of the power electronic switches. However, fast turn-off of the power electronic switches generates overvoltage in stray inductances of their high-frequency loop. It is thus often required to slow down the turn-off of the power electronic switches to protect them against overvoltage. This may seriously impact the overall efficiency of conventional power converter circuits.
FIG. 1 is an idealized circuit diagram of a conventional commutation cell such as those used in conventional power converter circuits. A commutation cell 10 converts a DC voltage Vbus from a voltage source 12 (or from a capacitor) into a current source Iout (or into an inductance) that usually generates a voltage Vout appropriate for a load 14, which may be a resistive load, an electric motor, and the like. The commutation cell 10 comprises a freewheel diode 16 and a controlled power electronic switch 18, for example an isolated gate bipolar transistor (IGBT). A capacitor 20 (Cin) is used to limit variations of the voltage Vbus of the voltage source 12 and an inductance 32 is used to limit the variations of the output current Iout. A gate driver (not shown in FIG. 1 but shown on later Figures) controls turning on and off of the power electronic switch 18. FIG. 1 illustrates a configuration of the commutation cell 10, of the load 14, and of the voltage source 12, in which energy flows from the voltage source 12 to the load 14, i.e. from left to right on the drawing. The commutation cell 10 can also be used in a reverse configuration in which energy flows in the opposite direction.
When turned on, the power electronic switch 18 allows current to pass therethrough, from its collector 22 to its emitter 24; at that time, the power electronic switch 18 can be approximated as a closed circuit. When turned off, the power electronic switch 18 does not allow current to pass therethrough and can be approximated as an open circuit.
The gate driver applies a variable control voltage between the gate 26 and the emitter 24 of the power electronic switch 18. For some types of power electronic switches such as bipolar transistors, the gate driver may act as a current source instead of as a voltage source. Generally, when the voltage applied between the gate 26 and the emitter 24 is “high”, the power electronic switch 18 allows passing of current from the collector 22 to the emitter 24. When the voltage applied between the gate 26 and the emitter 24 is “low”, the power electronic switch 18 blocks passage of current therethrough. In more details, a voltage difference between the gate 26 and the emitter 24, denoted Vge, is controlled by the gate driver. When Vge is greater than a threshold Vge(th) for the power electronic switch 18, the switch 18 is turned on and a voltage Vce between the collector 22 and the emitter 24 becomes near zero. When Vge is lower than Vge(th), the power electronic switch 18 is turned off and Vce eventually reaches Vbus.
When the power electronic switch 18 is turned on, a current Iout flows from the voltage source 12 (and transiently from the capacitor 20) through the load 14 and through the collector 22 and the emitter 24. When the power electronic switch 18 is turned off, the current Iout circulates from the load 14 and passes in the freewheel diode 16. It may thus be observed that the power electronic switch 18 and the freewheel diode 16 operate in tandem. Turning on and off of the power electronic switch 18 at a high frequency allows the current Iout, in the output inductance Lout 32, to remain fairly constant.
It should be observed that, in the case of other power electronic switch types, for example bipolar transistors, the term “gate” may be replaced with “base”, the base being controlled by a current as opposed to the gate that is controlled by a voltage. These distinctions do not change the overall operation principles of the commutation cell 10.
FIG. 2 is another circuit diagram of the conventional commutation cell of FIG. 1, showing parasitic (stray) inductances. In contrast with the idealized model of FIG. 1, connections between components of an actual commutation cell define parasitic inductances. Though the parasitic inductances are distributed at various places within the commutation cell 10, a suitable model presented in FIG. 2 shows two (2) distinct inductances representing the overall parasitic inductance, including an emitter inductance 30 of the power electronic switch 18 and an inductance 34 representative of all other parasitic inductances (other than the emitter inductance 30) around a high frequency loop 36 formed by the freewheel diode 16, the power electronic switch 18 and the capacitor 20. The high frequency loop 36 is a path where current changes significantly upon switching of the power electronic switch 18. It should be noted that an output inductance Lout 32 is not part of the high frequency loop because its current remains fairly constant through the commutation period.
FIG. 3 is a circuit diagram of an IGBT leg formed from two commutation cells. More specifically, two commutation cells 10 introduced in the above description of FIGS. 1-2, in which IGBTs are used as power electronic switches, are connected in a single loop and form an IGBT leg 50 powered with the voltage source 12 and capacitor 54. A first power electronic switch (bottom IGBT Q1) operates in tandem with a first freewheel diode (top freewheel diode D2) and a second power electronic switch (top IGBT Q2) operates in tandem with another freewheel diode (bottom freewheel diode D1). Each of the top and bottom IGBTs Q1, Q2 may actually include a plurality of parallelized IGBTs that are combined to provide additional power. Likewise, each of the top and bottom freewheel diodes D1, D2 may include a plurality of parallelized diodes. Parallelization of the IGBTs and of the diodes is not shown on FIG. 3 in order to simplify the illustration. In the context of the present disclosure, the terms “top” and “bottom” do not refer to a physical position of electronic devices in a circuit; these terms only refer to positions of electronic devices in a schematic representation as exemplified in FIG. 3. For example, without limiting the present disclosure, a device is considered located at the “top” when it is connected closer (in electrical terms) to a positive voltage source than to a negative voltage source. A device may be considered located at the “bottom” when it is connected to a negative voltage source with a lower impedance than to a positive voltage source.
Each IGBT has its own gate driver 52. A voltage source 12 provides a voltage Vbus in parallel to an input capacitance 54 (Cin) connected to the IGBT leg 50 via a parasitic inductance Lc. Inductances inherently provided in wires, connections, decoupling capacitor and circuit board traces of a power converter have been represented in FIG. 3. A three-phase power converter used for powering a three-phase electric motor (not shown) from a battery (also not shown), would comprise three (3) IGBT legs 50 as shown on FIG. 3. Since such power converters are believed well-known to those skilled in the art, they are not described in further details herein.
When the bottom IGBT Q1 is turned off, current transits from the bottom IGBT Q1 to the top freewheel diode D2, during an overvoltage period. Indeed, various parasitic inductances (Lc, L+Vbus, Lc-top, Le-top, Lc-bot, Le-bot and L−Vbus) present in a high frequency loop 51, formed by the IGBT leg 50 and the input capacitance 54, resist change of current therein, additive voltages develop in the high frequency loop 51 as illustrated by the polarities of the parasitic inductances shown on in FIG. 3. These voltages, added to the voltage Vbus of the source, often result in a voltage exceeding the maximal collector to emitter voltage Vce rating of the bottom IGBT Q1. The top IGBT Q2 is subject to the same problem.
Conventional solutions aim to limit overvoltage in power electronic switches by slowing down the slope of the gate-emitter voltage. However, excessive limitation of the overvoltage can imply longer switching times of the current, reducing commutation cell performance.
As can be seen from FIG. 3, the IGBT leg 50 has resistive dividers connected across some of the parasitic (stray) inductances of the high frequency loop 51. The IGBT leg 50 uses a compensation circuit that optimizes overvoltage on the IGBTs Q1, Q2 using the resistive dividers. Discussing the bottom portion of the IGBT leg 50 of FIG. 3, the bottom IGBT Q1 includes a parasitic collector inductance Lc-bot, a parasitic emitter inductance Le-bot. The gate 26 of the bottom IGBT Q1 connected to its gate driver 52 via a resistor R1. A reference 56 of the gate driver 52 is connected to a compensation circuit having a resistive divider circuit including two resistors R2 and R3 and, optionally, a diode D3 that may be added to allow the turn-on not to be impacted by shorting the resistor R2 when a voltage at the emitter of the bottom IGBT Q1 is higher than the reference 56. If present, the diode D3 is conducting while turning on the IGBT Q1 because the direction of the current in the IGBT Q1 causes a voltage to be higher at the emitter 24 than at the reference 56. In contrast, the diode D3 is not conducting while turning off the IGBT Q1 because a drop of voltage at the emitter 24 causes application of a negative voltage across the diode D3. It is to be noted that while the resistors R2 and R3 are shown connected across both parasitic inductances Le-bot and L−Vbus, they may alternatively be connected solely across parasitic inductance Le-bot, should this parasitic inductance be sufficient and the connection available.
In the circuit of FIG. 3, values of the resistors R2 and R3 are selected according to an acceptable overvoltage level allowed across the bottom IGBT Q1. A ratio of R2 over R3 is increased to reduce the overvoltage. The value of these two resistors R2 and R3 in parallel is set, in series with a gate driver resistor R1. A value of the gate driver resistor R1 is adjusted in a conventional manner according to a proper commutation behavior.
Values of the resistors of the compensation circuits are set to reduce the overvoltage caused by the presence of the emitter inductance on the IGBTs Q1, Q2. It is desired to tailor the overvoltage in order to reach the maximum IGBT rating while maintaining the speed of the di/dt for efficiency reasons. The voltage across the emitter parasitic inductance is thus split in two and only the voltage across the logical resistor is applied in the gate drive circuit to limit the gate voltage drop.
This technique works very well for the bottom IGBT Q1 because the emitter inductance Le-bot is sufficiently large to provide good overvoltage sampling. In contrast, for the top IGBT Q2, the emitter inductance Le-top often has a too small value to suitably clamp a voltage thereacross without increasing the gate resistor R4, to protect the top IGBT Q2. In practice, the emitter inductance Le-top of the top IGBT Q2 is very often too low to be used to bring down the overvoltage across the top IGBT Q2 to a safe level.
FIG. 4 is a schematic representation of a typical topology for an IGBT module. FIG. 5 is a top plan view of an actual IGBT module having the topology of FIG. 4, the IGBT module including a circuit card and a casing. Referring at once to FIGS. 4 and 5, a conventional IGBT module 100 includes a first set of parallelized IGBT 102 defining the top IGBT Q2 of FIG. 3 and their associated diodes 104, a second set of parallelized IGBT 106 defining the bottom IGBT Q1 and their associated diodes 108, a +Vbus tab 110, a −Vbus tab 112 and a load tab 114. Elements of the IGBT module 100 are mounted on a direct bonded copper (DBC) substrate 101. Because of the constraints on packaging of IGBT modules, the upper and lower IGBTs and diodes are often packaged in close proximity of each other, as shown on FIGS. 4 and 5.
In the example of FIGS. 4 and 5, four (4) IGBTs 102 are placed in parallel to form the top IGBT Q2 while four (4) more IGBTS 106 are placed in parallel to form the bottom IGBT Q1 of FIG. 3. Likewise, the top freewheel diode D2 and the bottom freewheel diode D1 are each realized as sets of four (4) parallelized diodes 104, 108. On FIGS. 4 and 5, the IGBTs and diodes are connected to traces of the DBC substrate 101. The tabs 110, 112 and 114 are mounted on the DBC substrate 101, itself mounted in a casing 103. On FIGS. 4 and 5, collectors 22 of the various IGBTs are not visible since they are mounted directly on DBC traces, including a c-top trace 116 and a c-bot trace 122. Emitters 24 are connected via wires 120 to an e-top trace 117 and to an e-bot trace 118 while gates 26 are connected to g-top and g-bot traces via wires 121. Likewise, cathodes of the various diodes are not visible, being directly mounted on the c-top 116 and c-bot 122 traces. Anodes of the various diodes are connected via wires 120 to the e-top 117 and to e-bot 118 traces.
In the IGBT module 100, interconnections made via DBC traces, wire bonds 120, 121 and external connections create the parasitic inductances introduced in the foregoing description of FIG. 3.
The e-bot trace 118 that forms a connection between the emitter 26 of the bottom IGBT Q1 (IGBTs 106) and the external connection of −Vbus tab 112 contains a zigzag pattern that create a fairly large parasitic inductance between these elements. Accordingly, a level of voltage across the emitter inductance Le-bot of the bottom IGBT Q1 can be injected in the gate driver 26 to of the bottom IGBT Q1 using the compensation circuit of FIG. 3 to create a negative voltage at its emitter 24, adequately slowing down the negative slope of the gate voltage.
In contrast, the wire bonds 120 interconnecting the emitter of the top IGBT Q2 (IGBTs 102) to the c-bot trace 122 of the bottom IGBT Q1 (IGBTs 106) are quite short. Therefore, the inductance between the emitter of the top IGBT Q2 and the collector of the bottom IGBT Q1 is quite small, in the order of a few nano-Henrys (nH). Accordingly, a level of voltage across the emitter inductance Le-top of the top IGBT Q2 that can be injected in the gate driver 26 of the top IGBT Q2 using the compensation circuit of FIG. 3 to create a negative voltage at its emitter 24 of the top IGBT Q2 to slow down the negative slope of the gate voltage may be too small to adequately limit the overvoltage of the top IGBT Q2.
The comparatively small value of the upper emitter inductance Le-top may impact the effectiveness of the solution described hereinabove when applied without additional modification to the top IGBT Q2.
Therefore, there is a need for a topology that provides a better definition of parasitic inductances in power electronic switches.